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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad8327 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 5 v catv line driver coarse step output power control functional block diagram diff or single input amp attenuation core z out = 75 8 8 8 z in (single) = 800 z in (diff) = 1.6k r1 r2 v out ad8327 daten data clk gnd (5 pins) txen sleep v cc (5 pins) v in+ v in vernier decode data latch shift register power-down logic power amp byp cxr features supports docsis standard for reverse path transmission gain programmable in 6.02 db steps over a 48.16 db range low distortion at 60 dbmv output C63 dbc sfdr at 21 mhz C57 dbc sfdr at 42 mhz output noise level C47 dbmv in 160 khz maintains 75 output impedance transmit enable and transmit disable modes upper bandwidth: 160 mhz (full gain range) 5 v supply operation supports spi interfaces applications gain-programmable line driver docsis high-speed data modems interactive cable set-top boxes pc plug-in cable modems general-purpose digitally controlled variable gain block general description the ad8327 is a low-cost, digitally controlled, variable gain amplifier optimized for coaxial line driving applications such as cable modems that are designed to the mcns-docsis upstream standard. an 8-bit serial word determines the desired output gain over a 48.16 db range resulting in gain changes of 6.02 db/major carry. the ad8327 comprises a digitally controlled variable attenuator of 0 db to 48.16 db, which is preceded by a low noise, fixed gain buffer and followed by a low distortion, high power amplifier. the ad8327 accepts a differential or single-ended input signal. the output is specified for driving a 75 ? load, such as coaxial cable. distortion performance of ?3 dbc is achieved with an output level up to 60 dbmv at 21 mhz bandwidth. a key performance and cost advantage of the ad8327 results from the ability to maintain a constant 75 ? output impedance during transmit enable and transmit disable conditions. in addition, this device has a sleep mode function that reduces the quiescent current to 5 ma. the ad8327 is packaged in a low-cost 20-lead tssop, oper ates from a single 5 v supply, and has an operatio nal temperature range of ?0 c to +85 c. fundamental frequency mhz 50 60 75 65 55 5 152535455565 distortion dbc 70 hd3 hd2 v out = 60dbmv @ max gain figure 1. harmonic distortion vs. frequency
rev. 0 C2C ad8327?pecifications (t a = 25 c, v s = 5 v, r l = 75 , v in(differential) = 30 dbmv) parameter conditions min typ max unit input characteristics specified ac voltage p out = 60 dbmv, max gain 30 dbmv noise figure max gain, f = 10 mhz 13.2 db input resistance single-ended input 800 ? differential input 1600 ? input capacitance 2pf gain control interface gain range 47.16 48.16 49.16 db maximum gain gain code = 10000000 (128 decimal) 29 30 31 db minimum gain gain code = 00000000 (0 decimal) ?9.16 ?8.16 ?7.16 db gain scaling factor 6.02 db/major carry output characteristics bandwidth (? db) all gain codes 160 mhz bandwidth roll-off f = 65 mhz 0.4 db bandwidth peaking all gain codes 0 db output noise spectral density max gain, f = 10 mhz ?2 dbmv in 160 khz min gain, f = 10 mhz ?7 dbmv in 160 khz transmit disable mode (txen = 0), 66 d bmv in f = 10 mhz 160 khz 1 db compression point max gain, f = 10 mhz 14.8 dbm differential output impedance transmit enable (txen = 1) and transmit disable mode (txen = 0) 75 20% ? overall performance second order harmonic distortion f = 21 mhz, v out = 60 dbmv @ max gain ?3 dbc f = 42 mhz, v out = 60 dbmv @ max gain ?1 dbc f = 65 mhz, v out = 60 dbmv @ max gain ?4 dbc third order harmonic distortion f = 21 mhz, v out = 60 dbmv @ max gain ?3 dbc f = 42 mhz, v out = 60 dbmv @ max gain ?7 dbc f = 65 mhz, v out = 60 dbmv @ max gain ?7 dbc adjacent channel power adjacent channel width = transmit channel ?2 dbc width = 160 k sym/sec gain linearity error f = 10 mhz, code to code 0.25 db output settling due to gain change (t gs ) min to max gain 60 ns due to input change max gain, v in = 30 dbmv 30 ns isolation in transmit disable mode max gain, txen = 0 v, f = 42 mhz, ?2 dbc v in = 30 dbmv power control transmit enable settling time (t on ) 1 max gain, v in = 0 v 300 ns transmit disable settling time (t off ) 1 max gain, v in = 0 v 40 ns transmit enable settling time (t on ) 2 max gain, v in = 0 v 2 s transmit disable settling time (t off ) 2 max gain, v in = 0 v 1.7 s between burst transients 2 equivalent output = 31 dbmv 3 mv p-p equivalent output = 60 dbmv 25 mv p-p ramp setting 2 2 s power supply operating range 4.75 5 5.25 v quiescent current transmit enable mode (txen = 1) @ dec 128 75 105 135 ma transmit enable mode (txen = 1) @ dec 0 40 60 80 ma transmit disable mode @ all gain codes 10 15 20 ma sleep mode @ all gain codes 3 5 7 ma operating temperature ?0 +85 c range notes 1 for transmit enable or transmit disable transitions using a 0 pf capacitor (at cxr pin) to ground. 2 for transmit enable or transmit disable transitions using a 100 pf capacitor (at cxr pin) to ground. specifications subject to change without notice.
rev. 0 C3C ad8327 logic inputs (ttl/cmos-compatible logic) parameter min typ max unit logic ??voltage 2.1 5.0 v logic ??voltage 0 0.8 v logic ??current (v inh = 5 v) clk, sdata, daten 020na logic ??current (v inl = 0 v) clk, sdata, daten ?00 ?00 na logic ??current (v inh = 5 v) txen 50 190 a logic ??current (v inl = 0 v) txen ?50 ?0 a logic ??current (v inh = 5 v) sleep 50 190 a logic ??current (v inl = 0 v) sleep ?50 ?0 a timing requirements parameter min typ max unit clock pulsewidth (t wh ) 16.0 ns clock period (t c ) 32.0 ns setup time sdata vs. clock (t ds ) 5.0 ns setup time daten vs. clock (t es ) 15.0 ns hold time sdata vs. clock (t dh ) 5.0 ns hold time daten vs. clock (t eh ) 3.0 ns input rise and fall times, sdata, daten , clock (t r , t f )10ns t es valid data word g1 msb. . . .lsb gain transfer (g1) t ds t eh 8 clock cycles gain transfer (g2) t off t gs analog output signal amplitude (p-p) txen clk sdata daten t on t c t wh valid data word g2 figure 2. serial interface timing valid data bit msb msb-1 msb-2 t ds t dh sdata clk figure 3. sdata timing (full temperature range, v cc = 5 v, t r = t f = 4 ns, f clk = 8 mhz unless otherwise noted.) ( daten , clk, sdata, txen, sleep , v cc = 5 v: full temperature range)
rev. 0 ad8327 C4C absolute maximum ratings * supply voltage +v s pins 4, 6, 11, 12, 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 v input voltages pins 17, 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 v pins 1, 2, 3, 19, 20 . . . . . . . . . . . . . . . . . . . ?.8 v to +5.5 v internal power dissipation tssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810 mw operating temperature range . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c lead temperature, soldering 60 seconds . . . . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configuration top view (not to scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 ad8327 daten v in v in+ gnd v cc sleep byp v cc v cc gnd sdata clk gnd v cc txen v cc v out gnd gnd cxr pin function descriptions pin no. mnemonic description 1 sdata serial data input. this digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the msb (most significant bit) first. 2 clk clock input. the clock port controls the serial attenuator data transfer rate to the 8-bit master- slave register. a logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. this requires the input serial data word to be valid at or before this clock transition. 3 txen logic ??disables transmission. logic ??enables transmission. 4, 6, 11, 12, 16 v cc common positive external supply voltage. a 0.1 f capacitor must decouple each pin. 5, 8, 9, 13, 15 gnd common external ground reference 7 cxr transmit enable/disable timing capacitor. this pin is decoupled with a 100 pf capacitor to gnd. 10 v out output signal 14 byp internal bypass. this pin must be externally ac-coupled (0.1 f capacitor). 17 v in+ nonin verting input. dc-biased to approximately v cc /2. should be ac-coupled with a 0.1 f capacitor. 18 v in inverting input. dc-biased to approximately v cc /2. should be ac-coupled with a 0.1 f capacitor. 19 sleep low power sleep mode. logic 0 enables sleep mode, where z out goes to 200 ? and supply current is reduced to 5 ma. logic 1 enables normal operation. 20 daten data enable low input. this port controls the 8-bit parallel data latch and shift register. a logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta- neously inhibits serial data transfer into the register. a 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8327 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide model temperature range package description ja package option ad8327aru ?0 c to +85 c 20-lead tssop 85 c/w * ru-20 ad8327aru-reel 40 c to +85 c 20-lead tssop 85 c/w * ru-20 AD8327-EVAL evaluation board * thermal resistance measured on semi standard 4-layer board.
rev. 0 v in+ v in gnd 0.1 f 165 v in 75 0.1 f ad8327 0.1 f 0.1 f 100pf v cc 10 f 0.1 f byp cxr +v s tpc 1. basic test circuit gain control decimal code 0.1 0 0.3 0.2 0.1 0.2 0.3 0.4 0.5 0.6 0 16 48 80 96 112 128 32 64 gain error db f = 65mhz f = 42mhz f = 5mhz f = 10mhz tpc 2. gain error vs. gain control frequency mhz 160 115 1 100 10 impedance v in+ v in 0.1 f 165 v in 0.1 f 75 0.1 f out gnd +v s ad8327 txen = 0 txen = 1 155 150 145 140 135 130 125 120 tpc 3. input impedance vs. frequency typical performance characteristics ad8327 C5C frequency mhz 0 10 90 1 1000 10 isolation dbc 100 20 30 70 40 50 60 80 txen = 0 v in = 30dbmv max gain min gain ),-* )
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$ frequency mhz 100 10 1000 1 10 20 30 0 10 20 30 40 gain db 128d 64d 32d 01d 16d 08d 04d 02d 00d ),-0 - frequency mhz 90 85 80 75 70 65 60 55 1 100 10 impedance txen = 0 txen = 1 ),-2 3 "
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rev. 0 ad8327 C6C fundamental frequency mhz 50 55 70 565 15 distortion dbc 25 35 45 55 60 65 v out = 61dbmv @ max gain v out = 60dbmv @ max gain v out = 59dbmv @ max gain v out = 58dbmv @ max gain tpc 7. second order harmonic distortion vs. frequency for various output levels gain control decimal code 50 55 90 0 128 16 distortion dbc 32 48 64 112 60 65 70 75 80 85 80 96 f o = 5mhz v out = 60dbmv @ max gain hd2 hd3 tpc 8. harmonic distortion vs. gain control gain control decimal code 70 80 75 65 60 55 50 85 90 048 32 64 16 distortion dbc 80 96 f o = 42mhz v out = 60dbmv @ max gain hd3 hd2 112 128 tpc 9. harmonic distortion vs. gain control v out = 60dbmv @ max gain fundamental frequency mhz 65 80 535 75 70 25 45 15 60 distortion dbc 55 65 v out = 59dbmv @ max gain v out = 61dbmv @ max gain v out = 58dbmv @ max gain 55 50 tpc 10. third order harmonic distortion vs. frequency for various output levels gain control decimal code 50 55 90 0 128 16 distortion dbc 32 48 64 112 60 65 70 75 80 85 80 96 f o = 21mhz v out = 60dbmv @ max gain hd2 hd3 tpc 11. harmonic distortion vs. gain control gain control decimal code 50 55 90 0 128 16 distortion dbc 32 48 64 112 60 65 70 75 80 85 80 96 f o = 65mhz v out = 60dbmv @ max gain hd2 hd3 tpc 12. harmonic distortion vs. gain control
rev. 0 ad8327 C7C 40 50 60 70 100 80 90 110 center 21mhz 75khz/div span 750khz c11 c0 c0 cu1 c11 ch pwr 9.0dbm acp up 62dbc acp low 62.5dbc cu1 30 20 10 tpc 13. adjacent channel power gain control decimal code 30 34 42 50 38 46 0 128 16 32 48 64 80 96 112 output noise dbmv in 160khz f = 10mhz txen = 1 tpc 14. output referred noise vs. gain control frequency mhz 35 30 10 1 1000 10 gain db 100 25 15 20 v in+ v in gnd 0.1 f 165 v in 75 0.1 f ad8327 0.1 f 0.1 f 100pf v cc 10 f byp cxr 0.1 f c l +v s c l = 20pf c l = 10pf c l = 0pf v out = 60dbmv @ max gain c l = 50pf tpc 15. ac response for various capacitor loads frequency mhz 60 40 20 40 10 41.0 43.0 41.2 41.4 41.8 42.0 42.2 42.4 42.6 42.8 41.6 v out dbmv v out = 60dbmv @ max gain 50 30 20 0 10 30 tpc 16. two-tone intermodulation distortion frequency mhz 25 75 30 45 55 60 70 40 565 15 25 35 45 55 output noise dbmv in 160khz @ max gain, txen = 1 35 50 65 @ min gain, txen = 1 all gain codes, txen = 0 tpc 17. output referred noise vs. frequency for various gain codes gain control decimal code 120 50 110 90 80 70 60 100 0 128 16 32 48 64 80 96 112 quiescent supply current ma txen = 1 tpc 18. supply current vs. gain code
rev. 0 ad8327 C8C applications general application the ad8327 is primarily intended for use as the upstream power amplifier (pa), also known as a line driver, in docsis (data over cable service interface specification) certified cable modems and catv set-top boxes. the upstream signal is either a qpsk or qam signal generated by a dsp, a dedicated qpsk/ qam modulator, or a dac. in all cases the signal must be low-pass filtered before being applied to the pa in order to filter out-of-band noise and higher order harmonics from the amplified signal. due to the varying distances between the cable modem and the headend, the upstream pa must be capable of varying the output power by applying gain or attenuation. the varying output power of the ad8327 ensures that the signal from the cable modem will have the proper level once it arrives at the headend. the upstream signal path commonly includes a diplexer and cable splitters. the ad8327 has been designed to overcome losses associated with these passive components in the upstream cable path. circuit description the ad8327 is composed of three analog functions in the power- up or forward mode. the input amplifier (preamp) can be used single-ended or differentially. if the input is used in the differen- tial configuration, it is imperative that the input signals be 180 degrees out of phase and of equal amplitude. the preamp stage drives a dac, which provides the ad8327? attenuation (eight bits or 48.16 db). the signals in the preamp and dac gain blocks are differential to improve the psrr and linearity. a differential current is fed from the dac into the output stage, which amplifies these currents to the appropriate levels necessary to drive a 75 ? load. the output stage maintains 75 ? output impedance, eliminating the need for external matching resistors. spi programming and gain adjustment the ad8327 is controlled through a serial peripheral interface (spi) of three digital data lines: clk, daten, and sdata. changing the gain requires eight bits of data to be streamed into the sdata port. the sequence of loading the sdata register begins on the falling edge of the daten pin, which activates the clk line. with the clk line activated, data on the sdata line is clocked into the serial shift register, most significant bit (msb) first, on the rising edge of the clk pulses. the 8-bit data word is latched into the attenuator core on the rising edge of the daten line. this provides control over the changes in the output signal level. the serial interface timing for the ad8327 is shown in figures 2 and 3. the programmable gain range of the ad8327 is ?8.16 db to +30 db with steps of 6.02 db per major carry. this provides a total gain range of 48.16 db. the ad8327 was characterized with a toko transformer (toko#617db-a0070) on the input, and the stated gain values account for the losses due to the transformer. table i shows the possible gain states. input bias, impedance, and termination the v in+ and v in inputs have a dc bias level of v cc /2, there fore the input signal should be ac-coupled using 0.1 f capacitors as seen in the typical application circuit (see figure 4). the differ- ential input impedance of the ad8327 is approximately 1.6 k ? , while the single-ended input impedance is 800 ? . table i. gain states decimal code bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gain 0 00000000 ?8.16 1 00000001 ?2.14 2 00000010 ?.12 4 00000100 ?.10 8 000010005.92 16 00010000 11.94 32 00100000 17.96 64 01000000 23.98 128 1000000030
rev. 0 ad8327 C9C single-ended inverting input when operating the ad8327 in a single-ended input mode v in+ and v in should be terminated as illustrated in figure 5. on the ad8327 evaluation boards, this termination method requires the removal of r13?16 and r20, as well as the addition of a 0 ? jumper at r17. table ii shows the correct values for r11 and r12 for some common input configurations. other input im ped- ance configurations may be accommodated using the equations in figure 5. the inverting and noninverting inputs of the ad8327 must be balanced for all input configurations + r11 r12 z in 800 800 z in r12 = ad8327 z in z in r12 r12 + z in r11 = figure 5. single-ended inverting input differential input from single-ended source the default configuration of the evaluation board implements a differential signal drive from a single-ended signal source. a toko 1:1 transformer is included on the board for this purpose (t3). enabling the evaluation board for single to differential input conversion requires r11?12 and r16?17 to be removed, and 0 ? jumpers must be installed on the placeholders for r14, r15, and r20. table ii provides typical r13 values for common input configurations. other input impedances may be calculated using the equation in figure 6. refer to figure 10 for evaluation board schematic. to utilize the transformer for converting a single- ended source into a differential signal, the input signal must be applied to v in+ . v in + r13 ad8327 r13 = z in 1600 1600 z in z in figure 6. single to differential input differential signal source the ad8327 evaluation board is also capable of accepting a differential input signal. remove r11?12, r14?15, and r20, and place 0 ? jumpers for r16?17. see table ii for common values of r13, or calculate other input configurations using the equation in figure 7. v in + ad8327 v in r13 z in r13 = z in 1600 1600 z in figure 7. differential input output bias, impedance, and termination the output of the ad8327 has a dc bias level of approximately v cc /2; therefore, it should be ac-coupled before being applied to the load. the output impedance of the ad8327 is internally maintained at 75 ? , regardless of whether the amplifier is in transmit enable or transmit disable mode. this eliminates the need for external back termination resistors. if the output signal is being evaluated using standard 50 ? test equipment, a mini- mum loss 75 ? to 50 ? pad must be used to provide the test circuit with the proper impedance match. sdata clk gnd v cc txen v cc cxr gnd gnd v out sleep v in v in+ byp v cc gnd gnd v cc v cc enb ad8327 10 f to diplexer z in = 75 txen sdata clk sleep enb 0.1 f 0.1 f 0.1 f 165 v in v in+ z in = 150 v cc 0.1 f 100pf 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f figure 4. typical application circuit
rev. 0 ad8327 C10C power supply the 5 v supply should be delivered to each of the v cc pins via a low impedance power bus to ensure that each pin is at the same potential. the power bus should be decoupled to ground using a 10 f tantalum capacitor located close to the ad8327aru. in addition to the 10 f capacitor, each v cc pin should be indi vidually decoupled to ground with 0.1 f ceramic chip capaci- tors located close to the pins. the bypass pin, labeled byp (pin 14), should also be decoupled with a 0.1 f capacitor. the pcb should have a low impedance ground plane covering all unused portions of the board, except in areas of the board where input and output traces are in close proximity to the ad8327. all ad8327 ground pins must be connected to the ground plane to ensure proper grounding of all internal nodes. cxr pin the ad8327 features internal circuitry that controls burst transients. this feature uses a 100 pf capacitor connected to pin 7 of the ad8327, to slow down the turn-on transient and minimize between-burst transients. signal integrity layout considerations careful attention to printed circuit board layout details will prevent problems due to board parasitics. proper rf design techniques are mandatory. the differential input and output traces should be kept as short as possible. it is also critical that all differential signal paths be symmetrical in length and width. in addition, the input and output traces should be kept far apart, to minimize coupling (crosstalk) through the board. following these guidelines will optimize the overall performance of the ad8327 in all applications. initial power-up when the supply voltage is first applied to the ad8327, the gain of the amplifier is initially set to gain code 0. as power is first applied to the amplifier, the txen pin should be held low (logic 0) to prevent forward signal transmission. after power has been applied to the amplifier, the gain can be set to the desired level by following the procedure provided in the spi programming and gain adjustment section. the txen pin can then be brought from logic 0 to logic 1, enabling forward signal transmission at the desired gain level. asynchronous power-down the asynchronous txen pin is used to place the ad8327 into between-burst mode, while maintaining a differential output impedance of 75 ? . applying logic 0 to the txen pin activates the on-chip reverse amplifier, providing an 86% reduction in consumed power. for 5 v operation, the supply current is typi cally reduced from 105 ma to 15 ma. in this mode of operation, between-burst noise is minimized and the amplifier can no longer transmit in the upstream direction. in addition to the txen pin, the ad8327 also incorporates an asynchronous sleep pin, which may be used to further reduce the supply current to approximately 5 ma. applying logic 0 to the sleep pin places the amplifier into sleep mode. transitioning into or out of sleep mode may result in a transient voltage at the output of the amplifier. distortion, adjacent channel power, and docsis in order to deliver the docsis required +58 dbmv of qpsk signal and +55 dbmv of 16 qam signal, the pa is required to deliver up to +60 dbmv and +57 dbmv respectively. this level is required to compensate for losses associated with the diplex filter or other passive components that may be included in the up stream path of cable modems or set-top boxes. it should be noted that the ad8327 was characterized with the toko 617db-a0070 transformer on the input to generate a differential input signal. tpc 7 and tpc 10 show the ad8327 second and third order harmonic distortion performance versus fundamental frequency for various output power levels. these figures are useful for determining the in-band harmonic levels from 5 mhz to 65 mhz. harmonics higher in frequency (above 42 mhz for docsis and above 65 mhz for eurodocsis) will be sharply attenuated by the low-pass filter function of the diplexer. another measure of signal integrity is adjacent channel power, commonly referred to as acp. docsis section 4.2.10.1.1 states, ?purious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or different symbol rates.?tpc 13 shows the measured acp for a +57 dbmv 16 qam signal taken at the output of the ad8327 evaluation board, through a 75 ? to 50 ? matching pad (5.7 db of loss). the transmit channel width and adjacent channel width in tpc 13 correspond to symbol rates of 160 k sym/s . table iii shows the acp results for the ad8327 driving a 16 qam, +57 dbmv signal for all conditions in docsis t able 4-7 ?djacent channel spurious emissions. table iii. adjacent channel power table ii. common input terminations differential input termination zin ( ) r11 r12 r13 ( ) 50 open open 52.1 75 open open 78.7 100 open open 107 150 open open 165 single-ended input termination zin ( ) r11 ( ) r12 ( ) r13 50 25.5 53.6 open 75 39.2 82.5 open 160 k sym/sec 320 k sym/sec 640 k sym/sec 1280 k sym/sec 2560 k sym/sec adjacent channel symbol rate transmit symbol rate 66 66 66 64 63 62 63 65 66 62 63 64 66 63 62 63 65 64 63 63 63 66 63 63 62 160 k sym/sec 320 k sym/sec 640 k sym/sec 1280 k sym/sec 2560 k sym/sec acp (dbc) acp (dbc) acp (dbc) acp (dbc) acp (dbc)
rev. 0 ad8327 C11C noise and docsis at minimum gain, the ad8327 output noise spectral density is 11 nv/ hz measured at 10 mhz. docsis table 4-8,?purious emissions in 5 mhz to 42 mhz,?specifies the output noise for various symbol rates. the calculated noise in dbmv for 160 ksym/second is: 20 11 160 60 47 2 log nv hz khz dbmv ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += comparing the computed noise power of 47 dbmv to the +8 dbmv signal yields 55 dbc, which meets the required level set forth in docsis table 4-8. as the ad8327 gain is increased above this minimum value, the output signal increases at a faster rate than the noise, resulting in a signal to noise ratio that improves with gain. in transmit disable mode, the output noise spectral density is 1.3 nv/ hz , which results in 66 dbmv when computed over 160 k sym/s . the noise power was measured directly at the output of the ad8327ar-eval board. evaluation board features and operation the ad8327 evaluation board (part #ad8327ar-eval) and control software can be used to control the ad8327 upstream cable driver via the parallel port of a pc. a standard printer cable connected between the parallel port of the personal com- puter is used to feed all the necessary data to the ad8327 using the windows-based control software. this package provides a means of evaluating the amplifier with a convenient way to program the gain/attenuation, as well as offering easy control of the asynchronous txen and sleep pins. with this evaluation kit, the ad8327 can be evaluated in either a single-ended or differential input configuration. a schematic of the evaluation board is provided in figure 10. overshoot on pc printer ports the data lines on some pc parallel printer ports have excessive overshoot that may cause communications problems when pre- sented to the clk pin of the ad8327. the evaluation board was designed to accommodate a series resistor and shunt capaci- tor (r2 and c5 in figure 10) to filter the clk signal if required. installing visual basic control software install the cabdrive_27 software by running setup.exe on disk one of the ad8327 evaluation software. follow on-screen directions and insert disk two when prompted. choose installa- tion directory, and then select the icon in the upper left to complete installation. running ad8327 software to load the control software, go to start, programs, cabdrive_27, or select the ad8327.exe from the installed directory. once loaded, select the proper parallel port to com- municate with the ad8327 (figure 8). figure 8. parallel port selection controlling gain/attenuation of the ad8327 the slide bar controls the gain/attenuation of the ad8327, which is displayed in db and in v/v. the gain scales 6 db per major carry. the gain code from the position of the slide bar is displayed in decimal, binary, and hexadecimal (figure 9). figure 9. control software interface
rev. 0 ad8327 C12C transmit enable and sleep mode the transmit enable and transmit disable buttons select the mode of operation of the ad8327 by asserting logic levels on the asynchronous txen pin. the transmit disable button applies logic 0 to the txen pin, disabling forward transmis- sion while maintaining a 75 ? back termination. the transmit enable button applies logic 1 to the txen pin, enabling the ad8327 for forward transmission. checking the enable sleep mode checkbox applies logic 0 to the asynchronous sleep pin, setting the ad8327 for sleep mode. memory functions the memory section of the software provides a way to alternate between two gain settings. the x->m1 button stores the current value of the gain slide bar into memory while the rm1 button recalls the stored value, returning the gain slide bar to the stored level. the same applies to the x->m2 and rm2 buttons. figure 10. evaluation board schematic z1 tssop20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 agnd t4 t3 6 1 2 3 4 5 4 3 2 1 toko1 sec pri sec pri dni c10 0.1 f c7 0.1 f agnd p1 19 p1 20 p1 21 p1 22 p1 23 p1 24 p1 25 p1 26 p1 27 p1 28 p1 29 p1 30 p1 31 p1 32 p1 33 p1 34 p1 35 p1 36 p1 1 p1 2 p1 3 p1 4 p1 5 p1 6 p1 7 p1 8 p1 9 p1 10 p1 11 p1 12 p1 13 p1 14 p1 15 p1 16 p1 18 p1 17 agnd c6 dni r3 0 tp7 tp8 c5 dni r2 0 tp5 tp6 c4 dni r1 0 tp3 tp4 tp2 c1 0.1 f c2 0.1 f c3 100pf tp1 sdata daten txen sleep clk agnd tp9 v cc agnd v cc tp12 tp10 tp11 c11 0.1 f c12 10 f agnd agnd c15 0.1 f r11 dni r12 dni r13 78.7 c16 0.1 f tp23 tp24 r14 0 r15 0 r16 dni r17 dni r19 dni agnd agnd tp22 0 hpp com lpp cbl 1 3 5 9 tp21 tp20 agnd r8 dni r9 0 r10 dni agnd cable cx6002 10 18 hpf v in+ r20 0 v in r21 dni agnd r7 0 r6 dni device = 2lugpwr tb1 agnd c8 0.1 f tp14 tp16 c14 0.1 f r5 dni tp15 daten v in v in+ gnd v cc sleep byp v cc v cc gnd sdata clk gnd v cc txen v cc v out gnd gnd cxr dni
rev. 0 ad8327 C13C figure 11. evaluation board layouttop silkscreen
rev. 0 ad8327 C14C figure 12. evaluation board layoutcomponent side
rev. 0 ad8327 C15C figure 13. evaluation board layoutinternal ground plane
rev. 0 ad8327 C16C figure 14. evaluation board layoutinternal power and ground plane
rev. 0 ad8327 C17C figure 15. evaluation board layoutcircuit side
rev. 0 ad8327 C18C figure 16. evaluation board layoutbottom silkscreen
rev. 0 ad8327 C19C evaluation board bill of materials ad8327 evaluation board rev. b, single-ended-to-differential input revised february 21, 2001 qty. description ref description 1 10 f 25 v. d size tantalum chip capacitor c12 1 100 pf 0603 ceramic chip capacitor c3 2 0.1 f 50 v. 1206 size ceramic chip capacitor c15, c16 7 0.1 f 25 v. 0603 size ceramic chip capacitor c1, c2, c7 c11 11 0 ? 5% 1/8 w. 1206 size chip resistor r1 r3, r7, r9, r14, r15, r20 1 78.7 ? 1% 1/8 w. 1206 size chip resistor r13 2 yellow test point tp23, tp24 1 red test point tp9 1 black test point tp10 tp12 (gnd) 1 centronics-type 36-pin right-angle connector p1 1 terminal block 2-pos green ed1973-nd tb1 4 sma end launch jack (e f johnson # 142-0701-801) v in , v in+ , cable_0, hpf 1 1:1 transformer toko # 617db a0070 t3 1 pulse diplexer * z2 1 ad8327 (tssop) upstream cable driver z1 1 ad8327 rev. c evaluation pc board evaluation pc board 4#4 40 1/4 inch stainless panhead machine screw 4#4 40 3/4 inch long aluminum round stand-off 2# 2 56 3/8 inch stainless panhead machine screw (p1 hardware) 2 # 2 steel flat washer (p1 hardware) 2 # 2 steel internal tooth lockwasher (p1 hardware) 2 # 2 stainless steel hex. machine nut (p1 hardware) notes * pulse diplexer part numbers b5008 (42 mhz), cx6002 (42 mhz), b5009 (65 mhz). do not install c4, c5, c6, r6, r7, r8, r10 r12, r16, r17, r21, t9, tp1 tp8, tp14 tp16, tp20 tp22. sma s txen, clk, sleep, daten, sdata, hpf_0, z2.
rev. 0 C20C c02653C.8C10/01(0) printed in u.s.a. ad8327 outline dimensions dimensions shown in inches and (mm). 20-lead tssop (ru-20) 20 1 11 10 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 0.260 (6.60) 0.252 (6.40) seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0

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